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1 ? fn7103.9 el8100, el8101 200mhz rail-to-rail amplifiers the el8100 and el8101 represent single rail-to-rail amplifiers with a -3db bandwidth of 200mhz and slew rate of 200v/s. running off a very low 2ma supply current, the el8100 and el8101 also feature inputs that go to 0.15v below the v s - rail. the el8100 includes a fast-acting disable/power-down circuit. with a 25ns disable and a 200ns enable, the el8100 is ideal for multiplexing applications. the el8100 and el8101 are designed for a number of general purpose video, communica tion, instrumentation, and industrial applications. the el8100 is available in 8 ld so and 6 ld sot-23 packages and the el8101 is available in a 5 ld sot-23 package. all are specified for operation over the -40c to +85c temperature range. features ? 200mhz -3db bandwidth ? 200v/s slew rate ? low supply current = 2ma ? supplies from 3v to 5.0v ? rail-to-rail output ? input to 0.15v below v s - ? fast 25ns disable (el8100 only) ?low cost ? pb-free (rohs compliant) applications ? video amplifiers ? portable/hand-held products ? communications devices pinouts el8100 (8 ld soic) top view el8100 (6 ld sot-23) top view el8101 (5 ld sot-23) top view ordering information part number (note 1) part marking package pkg. dwg. # el8100isz 8100isz 8 ld soic (pb-free) m8.15e el8100isz-t7* 8100isz 8 ld soic (pb-free) m8.15e el8100isz-t13* 8100isz 8 ld soic (pb-free) m8.15e EL8100IWZ-T7* basa (note 2) 6 ld sot-23 (pb-free) p6.064a EL8100IWZ-T7a* basa (note 2) 6 ld sot-23 (pb-free) p6.064a el8101iwz-t7* bata (note 2) 5 ld sot-23 (pb-free) p5.064a el8101iwz-t7a* bata (note 2) 5 ld sot-23 (pb-free) p5.064a *please refer to tb347 for detai ls on reel specifications. notes: 1. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin pl ate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak re flow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 2. the part marking is located on the bottom of the part. 1 2 3 4 8 7 6 5 - + nc in- in+ vs- enable vs+ out nc 1 2 3 6 4 5 - + out vs- in+ vs+ enable in- 1 2 3 5 4 - + out vs- in+ vs+ in- data sheet september 14, 2010 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2003-2005, 2007, 2010. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn7103.9 september 14, 2010 important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unles s otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute m aximum ratings (t a = +25c) thermal information supply voltage from v s + to v s - . . . . . . . . . . . . . . . . . . . . . . . . 5.5v input voltage . . . . . . . . . . . . . . . . . . . . . . . . v s + +0.3v to v s - -0.3v differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2v continuous output current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ma esd tolerance human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300v power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +125c ambient operating temperature . . . . . . . . . . . . . . . .-40c to +85c operating junction temperature . . . . . . . . . . . . . . . . . . . . . . +125c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. electrical specifications v s + = 5v, v s - = gnd, t a = +25c, v cm = 2.5v, r l to 2.5v, a v = 1, unless otherwise specified. parameter description conditions min (note 3) typ max (note 3) unit input characteristics v os offset voltage -6 -0.8 +6 mv tcv os offset voltage temperature coefficient measured from t min to t max 3v/c ib input bias current v in = 0v -2.1 -1.5 a i os input offset current v in = 0v 0.2 0.55 a tci os input bias current temperature coefficient measured from t min to t max 2na/c cmrr common mode rejection ratio v cm = -0.15v to +3.5v 70 90 db cmir common mode input range v s - -0.15 v s + -1.5 v r in input resistance common mode 16 m c in input capacitance 0.5 pf a vol open loop gain v out = +1.5v to +3.5v, r l = 1k to gnd 75 90 db v out = +1.5v to +3.5v, r l = 150 to gnd 80 db output characteristics r out output resistance a v = +1 30 m v op positive output voltage swing r l = 1k 4.85 4.9 v r l = 150 4.6 4.7 v v on negative output voltage swing r l = 150 100 150 mv r l = 1k 35 50 mv i out linear output current 65 ma i sc (source) short circuit current r l = 10 60 70 ma i sc (sink) short circuit current r l = 10 120 140 ma power supply psrr power supply rejection ratio v s + = 4.5v to 5.5v 75 100 db i s-on supply current - enabled 22.4ma i s-off supply current - disabled 30 a enable (el8100 only) t en enable time 200 ns t ds disable time 25 ns el8100, el8101
3 fn7103.9 september 14, 2010 v ih-enb enable pin voltage for power-up 0.8 v v il-enb enable pin voltage for shut-down 2 v i ih-enb enable pin input current high 8.6 a i il-enb enable pin input for current low 0.01 a ac performance bw -3db bandwidth a v = +1, r f = 0 , c l = 5pf 200 mhz a v = -1, r f = 1k , c l = 5pf 90 mhz a v = +2, r f = 1k , c l = 5pf 90 mhz a v = +10, r f = 1k , c l = 5pf 10 mhz bw 0.1db bandwidth a v = +1, r f = 0 , c l = 5pf 20 mhz peak peaking a v = +1, r f = 1k , c l = 5pf 1 db gbwp gain bandwidth product 100 mhz pm phase margin r l = 1k , c l = 5pf 55 sr slew rate a v = 2, r l = 100 , v out = 0.5v to 4.5v 160 200 v/s t r rise time 2.5v step , 20% to 80% 8 ns t f fall time 2.5v step , 20% to 80% 7 ns os overshoot 200mv step 10 % t pd propagation delay 200mv step 2 ns t s 0.1% settling time 200mv step 20 ns dg differential gain a v = +2, r f = 1k , r l = 150 0.035 % dp differential phase a v = +2, r f = 1k , r l = 150 0.05 e n input noise voltage f = 10khz 10 nv/ hz i n + positive input noise current f = 10khz 1 pa/ hz i n - negative input noise current f = 10khz 0.8 pa/ hz note: 3. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. electrical specifications v s + = 5v, v s - = gnd, t a = +25c, v cm = 2.5v, r l to 2.5v, a v = 1, unless otherwise specified. (continued) parameter description conditions min (note 3) typ max (note 3) unit pin descriptions pin number pin name description el8100is (8 ld soic) el8100iw (6 ld so- 23) el8101iw 5 ld sot-23) 1, 5 nc not connected 2 4 4 in- inverting input 3 3 3 in+ non-inverting input 4 2 2 vs- negative power supply 6 1 1 out amplifier output 7 6 5 vs+ positive power supply 85 enable enable and disable input el8100, el8101
4 fn7103.9 september 14, 2010 simplified schematic diagram in+ in- i 1 i 2 r 6 r 3 r 1 r 2 q 1 q 2 r 7 v bias1 q 5 q 6 r 8 q 7 q 8 r 9 q 3 q 4 r 4 r 5 v s- out v bias2 v s+ differential to drive generator single ended typical performance curves figure 1. frequency respo nse for various output voltage levels figure 2. small signal frequency response for various r load figure 3. small signal frequency response for various non-inverting gains figure 4. small signal frequency response for various inverting gains 4 2 0 -2 -4 -6 100k 1m 10m 100m 1g frequency (hz) gain (db) v s = 5v a v = 1 r l = 1k c l = 5pf v op-p = 200mv v op-p = 1v v op-p = 2v 4 2 0 -2 -4 -6 100k 1m 10m 100m 1g frequency (hz) gain (db) v s = 5v a v = 1 c l = 5pf r l = 330 r l = 1k r l = 100 4 2 0 -2 -4 -6 100k 1m 10m 100m 1g frequency (hz) normalized gain (db) v s = 5v r l = 1k c l = 5pf a v = 1 a v = 10 a v = 5 a v = 2 4 2 0 -2 -4 -6 100k 1m 10m 100m 1g frequency (hz) normalized gain (db) v s = 5v r l = 1k c l = 5pf r f = 1k a v = -10 a v = -2 a v = -5 el8100, el8101
5 fn7103.9 september 14, 2010 figure 5. small signal frequency response for various c l figure 6. small signal frequency response for various c l figure 7. small signal frequency response for various r f and r g figure 8. open loop gain and phase vs frequency figure 9. common-mode rejection ratio vs frequency figure 10. small signal bandwidth vs supply voltage typical performance curves (continued) 5 3 1 -1 -3 -5 100k 1m 10m 100m 1g frequency (hz) gain (db) v s = 5v a v = 1 r l = 1k v op-p = 200mv c l = 15pf c l = 1.5pf c l = 11.5pf c l = 8.3pf c l = 5pf 10 8 6 4 2 0 100k 1m 10m 100m 1g frequency (hz) gain (db) c l = 15pf c l = 5pf c l = 56pf c l = 35pf v s = 5v a v = 2 r l = 1k r f = r g = 1k 10 8 6 4 2 0 100k 1m 10m 100m 1g frequency (hz) gain (db) v s = 5v a v = 2 r l = 1k c l = 5pf r f = r g = 2k r f = r g = 500 r f = r g = 1k 110 70 30 -10 -50 -90 1k 10k 1m 100m 1g frequency (hz) gain (db) r l = 1k phase () -45 405 315 225 135 45 100k 10m r l = 150 r l = 150 r l = 1k -10 -30 -50 -70 -90 -110 100k 1m 10m 100m frequency (hz) cmrr (db) 230 170 130 210 70 50 3.03.5 4.55.05.5 v s (v) bandwidth (mhz) r l = 1k c l = 5pf a v = 1 a v = 2 190 110 90 150 4.0 el8100, el8101
6 fn7103.9 september 14, 2010 figure 11. output impedance vs frequency figure 12. small signal peaking vs supply voltage figure 13. power supply rejection ratio vs frequency figure 14. harmonic distortion vs output voltage figure 15. disabled output isolation frequency response figure 16. harmonic distortion vs frequency typical performance curves (continued) 100 10 1.0 0.1 0.01 10k 100k 1m 10m frequency (hz) impedance ( ) 100m 2.5 1.0 2.0 0 3.03.5 4.55.05.5 v s (v) peaking (db) a v = 1 r l = 1k c l = 5pf 1.5 0.5 4.0 -10 -30 -50 -70 -90 -110 1k 10k 10m 100m frequency (hz) psrr (db) 100k 1m psrr- psrr+ -45 -65 -75 -55 -95 15 v op-p (v) distortion (dbc) v s = 5v r l = 1k c l = 5pf a v = 2 -85 34 2 h d 2 @ 1 0 m h z h d 3 @ 1 0 m h z h d 3 @ 5 m h z h d 2 @ 5 m h z h d 2 @ 1 m h z hd3@1mhz -10 -30 -50 -70 -90 -110 1k 10k 1m 100m 1g frequency (hz) gain (db) v s = 5v a v = 1 r l = 1k c l = 5pf 10m 100k -30 -50 -80 -40 -100 140 frequency (mhz) distortion (dbc) v s = 5v r l = 1k v o = 1v p-p for a v = 1 v o = 2v p-p for a v = 2 -90 10 h d 2 @ a v = 2 -70 -60 h d 2 @ a v = 1 h d 3 @ a v = 2 h d 3 @ a v = 1 el8100, el8101
7 fn7103.9 september 14, 2010 figure 17. harmonic distortion vs load resistance figure 18. voltage and current noise vs frequency figure 19. large signal transient response figure 20. output swing figure 21. small signal transient response figure 22. output swing typical performance curves (continued) -60 -75 -90 -65 -100 100 2k r load ( ) distortion (dbc) -95 1k v s = 5v v o = 1v p-p for a v = 1 v o = 2v p-p for a v = 2 -70 -85 -80 h d 2 @ a v = 2 h d 2 @ a v = 1 h d 3 @ a v = 2 h d 3 @ a v = 1 1.0k 1.0 100 0.1 10 100 10k 100k 10m frequency (hz) voltage noise (nv/ hz) current noise (pa/ hz) e n 10 1k 1m i n + i n - v s = 5v, a v = 1, r l = 1k to 2.5v 10ns/div 0 5.0 2.5 v s = 5v, a v = 5, r l = 1k to 2.5v 2s/div 0 5.0 2.5 v s = 5v, a v = 1, r l = 1k to 2.5v c l = 5pf 10ns/div 2.4 2.5 2.6 v s = 5v, a v = 5, r l = 1k to 2.5v 2s/div 0 5.0 2.5 el8100, el8101
8 fn7103.9 september 14, 2010 description of operat ion and application information product description the el8100, el8101 are wide bandwidth, single supply, low power and rail-to-rail output voltage feedback operational amplifiers. both amplifiers are internally compensated for closed loop gain of +1 of greater. connected in voltage follower mode and driving a 1k load, the el8100, el8101 have a -3db bandwidth of 200mhz. driving a 150 load, the bandwidth is about 130mhz while maintaining a 200v/s slew rate. the el8100 is available with a power-down pin to reduce power to 30a typically while the amplifier is disabled. input, output and supply voltage range the el8100, el8101 have been designed to operate with a single supply voltage from 3v to 5.0v. split supplies can also be used as long as their total voltage is within 3v to 5.0v. the amplifiers have an input common mode voltage range from 0.15v below the negative supply (vs- pin) to within 1.5v of the positive supply (vs+ pin). if the input signal is outside the above specified range, it will cause the output signal to be distorted. the output of the el8100, el8101 can swing rail-to-rail. as the load resistance becomes lower, the ability to drive close to each rail is reduced. for the load resistor 1k , the output swing is about 4.9v at a 5v supply. for the load resistor 150 , the output swing is about 4.6v. choice of feedback resistor and gain bandwidth product for applications that require a gain of +1, no feedback resistor is required. just short the output pin to the inverting input pin. for gains greater than +1, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. as this pole becomes smaller, the amplifier?s phase margin is reduced. this causes ringing in the time domain figure 23. disabled respons e figure 24. enabled response figure 25. package power dissipation vs ambient temperature figure 26. package power dissipation vs ambient temperature typical performance curves (continued) v s = 2.5v, a v = 1, r l = 1k ch1, ch2, 0.5v/div, m = 20ns ch2 ch1 enable input output v s = 2.5v, a v = 1, r l = 1k ch1, ch2, 1v/div, m = 100ns ch2 ch1 enable input v out 909mw 1.4 1.2 1.0 0.8 0.6 0.2 0 0 25 50 75 100 150 125 85 jedec jesd51-7 high effective thermal conductivity test board 0.4 ambient temperature (c) power dissipation (w) 435mw so8 ja = +110c/w sot23-5/6 ja = +230c/w 1.0 0.9 0.8 0.6 0.4 0.1 0 0 25 50 75 100 150 ambient temperature (c) power dissipation (w) 125 85 jedec jesd51-3 low effective thermal conductivity test board 0.2 0.7 0.3 0.5 625mw so8 ja = +160c/w sot23-5/6 ja = +256c/w 391mw el8100, el8101
9 fn7103.9 september 14, 2010 el8100, el8101 and peaking in the frequency domain. therefore, r f has some maximum value that should not be exceeded for optimum performance. if a large value of r f must be used, a small capacitor in the few pico farad range in parallel with r f can help to reduce the ringing and peaking at the expense of reducing the bandwidth. as far as the output stage of the amplifier is concerned, the output stage is also a gain stage with the load. r f and r g appear in parallel with r l for gains other than +1. as this combination gets smaller, the bandwidth falls off. consequently, r f also has a minimum value that should not be exceeded for optimum performance. for gain of +1, r f = 0 is optimum. for the gains other than +1, optimum response is obtained with r f between 300 to 1k . the el8100, el8101 have a gain bandwidth product of 100mhz. for gains 5, its bandwidth can be predicted by equation 1: video performance for good video performance, an amplifier is required to maintain the same output impedance and the same frequency response as dc levels are changed at the output. this is especially difficult when driving a standard video load of 150 , because the change in output current with dc level. special circuitry has been incorporated in the el8100, el8101 to reduce th e variation of the output impedance with the current output. this results in dg and dp specifications of 0.03% and 0.05 , while driving 150 at a gain of 2. driving high impedance loads would give a similar or better dg and dp performance. driving capacitive loads and cables the el8100, el8101 can drive 15pf loads in parallel with 1k with less than 5db of peaking at gain of +1. if less peaking is desired in applications, a small series resistor (usually between 5 to 50 ) can be placed in series with the output to eliminate most peaking. however, this will reduce the gain slightly. if the gain sett ing is greater than 1, the gain resistor r g can then be chosen to make up for any gain loss which may be created by the additional series resistor at the output. when used as a cable driver, double termination is always recommended for reflection-free performance. for those applications, a back-termination series resistor at the amplifier?s output will isolate th e amplifier from the cable and allow extensive capacitive drive. however, other applications may have high capacitive loads without a back-termination resistor. again, a small series resistor at the output can help to reduce peaking. disable/power-down the el8100 can be disabled and placed its output in a high impedance state. the turn-off time is about 25ns and the turn-on time is about 200ns. when disabled, the amplifier?s supply current is reduced to 30a typically, thereby effectively eliminating the power consumption. the amplifier?s power-down can be controlled by standard ttl or cmos signal levels at the enable pin. the applied logic signal is relative to v s - pin. letting the enable pin float or applying a signal that is less than 0.8v above v s - will enable the amplifier. the amplifier will be disabled when the signal at the enable pin is 2v above v s -. output drive capability the el8100, el8101 do not have internal short circuit protection circuitry. they have a typical short circuit current of 70ma sourcing and 140ma sinking for the output is connected to half way between the rails with a 10 resistor. if the output is shorted indefi nitely, the power dissipation could easily increase such that the part will be destroyed. maximum reliability is maintained if the output current never exceeds 40ma. this limit is set by the design of the internal metal interconnections. power dissipation with the high output drive cap ability of the el8100, el8101, it is possible to exceed the +125 c absolute maximum junction temperature under certain load current conditions. therefore, it is im portant to calculate the maximum junction temperature for the applicatio n to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. the maximum power dissipation allowed in a package is determined according to equation 2: where: t jmax = maximum junction temperature t amax = maximum ambient temperature ja = thermal resistance of the package the maximum power dissipation actually produced by an ic is the total quiescent supply current times the total power supply voltage, plus the power in the ic due to the load, or: for sourcing, equation 3: for sinking, equation 4: where: v s = total supply voltage i smax = maximum quiescent supply current gain bw 100mhz = (eq. 1) pd max t jmax t amax ? ja -------------------------------------------- - = (eq. 2) pd max v s i smax v s v out ? () v out r l --------------- - + = (eq. 3) pd max v s i smax v out v s - ? () i load + = (eq. 4)
10 fn7103.9 september 14, 2010 v out = maximum output voltage of the application r load = load resistance tied to ground i load = load current by setting the two pd max equations equal to each other, we can solve the output current and r load to avoid the device overheat. power supply bypassing and printed circuit board layout as with any high frequency device, a good printed circuit board layout is necessary for optimum performance. lead lengths should be as sort as possible. the power supply pin must be well bypassed to reduce the risk of oscillation. for normal single supply operation, where the vs- pin is connected to the ground plane, a single 4.7f tantalum capacitor in parallel with a 0. 1f ceramic capacitor from v s + to gnd will suffice. this same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. in this case, the v s - pin becomes the negative supply rail. for good ac performance, parasitic capacitance should be kept to a minimum. use of wi re-wound resistors should be avoided because of their additional series inductance. use of sockets should also be avoided if possible. sockets add parasitic inductance and capacitance that can result in compromised performanc e. minimizing parasitic capacitance at the amplifier?s inverting input pin is very important. the feedback resistor should be placed very close to the inverting input pin. strip line design techniques are recommended for the signal traces. typical applications video sync pulse remover many cmos analog to digital converters have a parasitic latch up problem when subjected to negative input voltage levels. since the sync tip contains no useful video information and it is a negativ e going pulse, we can chop it off. figure 27 shows a gain of 2 connections for el8100, el8101. figure 28 shows the complete input video signal applied at the input, as well as the output signal with the negative going sync pulse removed. multiplexer besides the normal power-down usage, the enable pin of the el8100 can be used for multiplexing applications. figure 29 shows two el8100s with the outputs tied together, driving a back terminated 75 video load. a 2v p-p 2mhz sine wave is applied to amp a and a 1v p-p 2mhz sine wave is applied to amp b. figure 30 shows the enable signal and the resulting output waveform at v out . observe the break-before-make operation of the multiplexing. amp a is on and v in1 is passed through to the output when the enable signal is low and turns off in about 25ns when the enable signal is high. about 200ns later, amp b turns on and v in2 is passed through to the output. the break-before-make operation ensures that more than one amplifier isn?t trying to drive the bus at the same time. figure 27. sync pulse remover 5v 1k v out v in 75 + - 75 1k 75 v s+ v s- figure 28. video signal 1.0v 0.5v 0v 1.0v 0.5v 0v m = 10s/div v out v in figure 29. two to one multiplexer +2.5v 1k 2mhz 75 + - 1k 75 -2.5v v out 75 1v p-p b +2.5v 1k 2mhz + - 1k 75 -2.5v 2v p-p a enable el8100, el8101
11 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7103.9 september 14, 2010 single supply video line driver the el8100, el8101 are wideband rail-to-rail output op amplifiers with large output current, excellent dg, dp, and low distortion that allow them to dr ive video signals in low supply applications. figure 31 is the single supply non-inverting video line driver configuration and figure 32 is the inverting video ling driver configuration. the signal is ac-coupled by c 1 . r 1 and r 2 are used to level shift the input and output to provide the largest output swing. r f and r g set the ac gain. c 2 isolates the virtual ground potential. r t and r 3 are the termination resistors for the line. c 1 , c 2 and c 3 are selected big enough to minimize the droop of the luminance signal. figure 30. enable signal 0v -0.5v -1.5v -2.5v 1v 0v m = 50ns/div a enable b -1v figure 31. 5v single supply non inverting video line driver 5v r f v out v in 75 + - 75 1k 75 c 3 470f r 3 c 1 47f r t 10k 10k r 2 r 1 1k r g c 2 220f figure 32. 5v single supply inverting video line driver 5v r f v out v in 75 - + 75 500 75 c 3 470f r 3 c 1 47f r t 10k 10k r 2 r 1 1k r g c 2 220f 5v figure 33. video line driver frequency response 5 4 3 2 1 0 -1 -2 -3 -4 -5 normalized gain (db) 100k 1m 10m 100m 200m frequency (hz) a v = -2 a v = 2 el8100, el8101
12 fn7103.9 september 14, 2010 el8100, el8101 package outline drawing m8.15e 8 lead narrow body small outline plastic package rev 0, 08/09 unless otherwise specified, tolerance : decimal 0.05 the pin #1 identifier may be either a mold or mark feature. interlead flash or protrusions shall not exceed 0.25mm per side. dimension does not include interlead flash or protrusions. dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "a" side view ?a typical recommended land pattern top view a b 4 4 0.25 a mc b c 0.10 c 5 id mark pin no.1 (0.35) x 45 seating plane gauge plane 0.25 (5.40) (1.50) 4.90 0.10 3.90 0.10 1.27 0.43 0.076 0.63 0.23 4 4 detail "a" 0.22 0.03 0.175 0.075 1.45 0.1 1.75 max (1.27) (0.60) 6.0 0.20 reference to jedec ms-012. 6. side view ?b?
13 fn7103.9 september 14, 2010 el8100, el8101 package outline drawing p5.064a 5 lead small outline transistor plastic package rev 0, 2/10 dimension is exclusive of mold flash, protrusions or gate burrs. this dimension is measured at datum ?h?. package conforms to jedec mo-178aa. foot length is measured at reference to guage plane. dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "x" side view typical recommended land pattern top view index area pin 1 seating plane gauge 0.450.1 (2 plcs) 10 typ 4 1.90 0.40 0.05 2.90 0.95 1.60 2.80 0.05-0.15 1.14 0.15 0.20 c a-b d m (1.20) (0.60) (0.95) (2.40) 0.10 c 0.08-0.20 see detail x 1.45 max (0.60) 0-3 c b a d 3 3 3 0.20 c (1.90) 2x 0.15 c 2x d 0.15 c 2x a-b (0.25) h 5 2 4 5 5 end view plane
14 fn7103.9 september 14, 2010 el8100, el8101 package outline drawing p6.064a 6 lead small outline transistor plastic package rev 0, 2/10 1.60 0.08-0.20 see detail x (0.60) 0-3 3 5 detail "x" side view typical recommended land pattern top view end view index area pin 1 seating plane gauge 0.450.1 (2 plcs) 10 typ 4 1.90 0.40 0.05 2.90 0.95 2.80 0.05-0.15 1.14 0.15 0.20 c a-b d m (1.20) (0.60) (0.95) (2.40) 0.10 c 1.45 max c b a d 3 3 0.20 c (1.90) 2x 0.15 c 2x d 0.15 c 2x a-b (0.25) h 64 5 5 13 2 plane dimension is exclusive of mold flash, protrusions or gate burrs. this dimension is measured at datum ?h?. package conforms to jedec mo-178aa. foot length is measured at reference to guage plane. dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. 3. 5. 4. 2. dimensions are in millimeters. 1. notes:

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